1. Field of the Invention
The present invention relates to a fractional divider and, more particularly, to a low jitter fractional divider with low circuit speed constraint.
2. Description of Related Art Conventionally, a fractional divider is provided to divide the frequency of a clock signal by a fraction number "b/a", wherein b&gt;a. Such a fractional divider is implemented by employing an accumulator to add the value of "a" to the value stored in the accumulator in each operation cycle. The accumulated value is compared with the value of "b". In case of a&gt;b, the accumulated value is subtracted by the value of "b" and re-stored to the accumulator, and an overflow flag is generated. Otherwise, the accumulated value is simply re-stored to the accumulator. This overflow flag is provided to be the output of the fractional divider. FIG. 4 shows that such a fractional divider 41 is used to divide a clock signal "ck" by 5/3 to generate a divided clock signal "ck'". Based on the operating manner of the fractional divider 41 as described above, a timing diagram is obtained, which illustrates that five continuous pulses of the clock signal "ck" are applied to the fractional divider 41 to generate three continuous pulses of clock signal "ck'". Therefore, a divide-by-5/3 operation is performed. However, the pulses of the clock signal "ck'" generated by the fractional divider 41 are not uniformly distributed, which is known as a jitter phenomenon in the art. Such jitter is especially obvious if the clock frequency to be divided is low. To overcome this jitter problem, the conventional technique employs a high frequency base clock signal and an accumulator for implementing a fractional divider to obtain a low jitter clock signal. However, when the stages of the accumulators are increased and the frequency of the base clock signal goes higher, the accumulator will not be able to finish the required accumulation operation in a short operation cycle, due to the limitation imposed by the current integrated circuit manufacturing process. Accordingly, a bottleneck is encountered with the increase of a clock signal. In addition, it may be applicable to reduce the frequency of a high-frequency clock signal prior to performing the fractional division operation, thereby avoiding the bottleneck. Unfortunately, this will increase the jitter as described above. Therefore there is a need to have a fractional divider which can mitigate and/or obviate the aforementioned problems.